JFET IC Tech Guide

How to Design 500 °C Durable Integrated Circuits

Could your system benefit from integrated circuits durably operating for years in the most extreme environments? 

Given that accessibility and commercialization are key to new technology infusion, NASA Glenn prototypes developmental SiC JFET-R IC designs for interested external partners*. This NASA Glenn 500 °C Durable JFET IC Technical User Guide is intended to stimulate further exploratory design, simulation, and layout of potentially beneficial application-specific JFET-R ICs by new potential technology users. The technical overview on this page combined with linked technical primers should enable competent electrical engineers to design their own SiC JFET-R circuits for implementation in the next developmental IC run tentatively scheduled to start fabrication in 2023. A basic device Process Development Kit (PDK) for the NASA Glenn SiC JFET IC Generation 12 is also available, please contact Phil Neudeck if interested in receiving this PDK. 

*Note that all IC prototyping done at NASA Glenn requires a formal agreement negotiated by the NASA Glenn Technology Transfer Office. NASA-owned patents covering key aspects of the SiC IC technology are available for licensing. For further information about obtaining prototyping and technology licensing agreements, please contact Jeanne King of the NASA Glenn Technology Transfer Office. 

If you are interested in exploring this unique IC capability but do not wish to undertake the effort of circuit design, SiC JFET-R integrated circuit design services are commercially available (via existing technology agreement between Ozark Integrated Circuits, Inc. and NASA Glenn). 

Technical Design Primers

For those already somewhat familiar with the NASA Glenn 500 °C Durable IC JFET-R technology approach, the below technical primers communicate the specific mask layout rules and SPICE models that NASA Glenn is using as it designed its own SiC JFET-R integrated circuit prototypes.

NOTICE: There are two sets of design documents posted below, one for IC Generation 12 that is presently in fabrication and another document set for a more capable and advanced IC Generation 13 process that would start no earlier than 2023. IC Generation 13 advancements are technically enabled by anticipated switch to stepper-based lithography executed at non-NASA SiC fabrication foundry, which will permit substantially smaller alignment tolerance and feature size than fabrication using contact aligner lithography at NASA Glenn. If NASA Glenn does not receive sufficient funding for outsourcing the first 7 masks of the JFET-R process to stepper-tool lithography, Generation 12 design (posted online since April 2019) and contact aligner lithography will be re-employed during the next prototype SiC JFET-R IC fabrication run instead of below-posted Generation 13 design advancements.

IC Generation 12 Design Contact Aligner Photolithography	IC Generation 13 Design Stepper Tool Photolithography
IC Gen. 12 Mask Layout	IC Gen. 13 Mask Layout
IC Gen. 12 JFET SPICE Modeling	IC Gen. 13 JFET SPICE Modeling (Major Update Oct. 2023)
IC Gen. 12 Resistor SPICE Modeling	IC Gen. 13 Resistor SPICE Modeling
IC Gen. 12 SiC Epi-Wafer Specifications	IC Gen. 13 SiC Epi-Wafer Specifications

Technical Background 

For those not already familiar with NASA Glenn’s basic approach to realizing the world’s only ICs that have demonstrated thousands of hours of stable 500 °C operation, the following summary discourse and links provide important key background technical information. It should be noted that the linked publications are publicly published reports summarizing results from previous generations (through “Version 11”) of prototype NASA Glenn JFET IC wafer runs. 

Device Approach

JFETs and Resistors Based on SiC Epilayer Junctions

As described in the below publication link, NASA Glenn is implementing n-channel silicon carbide (SiC) Junction Field Effect Transistors and Resistors (JFET-R) as the most straightforward foundation for accomplishing integrated devices with inherent extreme-T immutability. While earlier work was conducted in the 6H-SiC crystal polytype, more recent NASA Glenn JFET-R IC work has transitioned to 4H-SiC wafers consistent with the expanding commercial SiC power device manufacturing base. 

Extreme Temperature 6H-SiC JFET Integrated Circuit Technology, Physica Status Solidi A, vol. 206, p. 2329 (2009).
See Sections 1.2 and 1.3 of this article regarding factors considered in technology selection. 

Fabrication Process Flow

Two levels of extremely durable tantalum silicide metal are used to interconnect basic JFET and resistor devices implemented in the SiC.

See slides 20-34 of the below link that illustrate the basic NASA Glenn IC SiC JFET-R fabrication process flow to the degree needed to accomplish circuit design and layout.
Processing and Characterization of Thousand-Hour 500 °C Durable 4H-SiC JFET Integrated Circuits, Presented at 2016 IMAPS High Temperature Electronics Conference.

In addition to integrated JFETs and resistors, this process flow also permits implementation of small-value (few pF) on-chip capacitors, as shown on slide 15 of the IC Generation 12 Mask Layout Primer. 

SPICE Modeling

The following links introduce NASA Glenn’s general approach to SPICE modeling of transistor and resistor devices. For reasons described in the linked publications, JFET device models change not only as a function of temperature, but also as a function of position on the SiC wafer. Circuit designs should therefore take both of these substantial device performance dependencies into account. To maximize technology accessibility, NASA Glenn JFET and resistor models are built from core device types/models available to all known versions of SPICE. It is important to note that the actual SPICE models stated in these publications are now obsolete, as they were based upon prior JFET-R IC generations. For updated SPICE models, please see the IC Generation 12 and 13 SPICE modeling document links in the above Technical Design Primers section.

The three links below introduce the modeling of integrated SiC JFETs using baseline NMOS Level 1 models available in all versions of SPICE.

• Experimental and Theoretical Study of 4H-SiC JFET Threshold Voltage Body Bias Effect from 25 °C to 500 °C, Materials Science Formum vol. 828, p. 903 (2016)
  
• First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits, Proc. 2016 High Temperature Electronics Conference, p. 263.
• First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits, Presented at 2016 High Temperature Electronics Conference.  

The below link introduce NASA Glenn’s approach to modeling integrated SiC resistors.

Inclusion of Body Bias Effect in SPICE Modeling of 4H-SiC Integrated Circuit Resistors, Materials Science Forum, vol. 924, p. 949 (2018).

In order to account for non-negligible substrate body-bias effects, NASA Glenn SPICE-models integrated SiC resistors using NMOS Level 1 transistor models as described in this paper. 

Circuit Design

While SiC JFETs and resistors have demonstrated excellent extreme-environment durability and stability, the n-channel depletion-mode nature of these devices dictates the use of non-standard IC power supply and signal voltage levels. Typical NASA Glenn SiC JFET logic ICs employ typically power supply voltages near +25 V for VDD and -25 V for VSS with signal input/output voltages around 0 V for logic “1” high and around -10 V for logic “0” low. It is important to note that the negative power supply bias -VSS is always applied to IC chip substrate backside. 

Slide 10 of the IC Generation 12 Mask Layout Primer illustrates the circuit schematic and layout of the basic IC Generation 12 NOT logic gate. This logic gate design is updated from prior logic gate circuit designs implemented in Version 10 and lower NASA Glenn prototype ICs. 

A major benefit of integrating SiC resistors with SiC transistors is that these devices exhibit nearly identical temperature dependence of electrical conductivity that enables JFET ICs to function over very large temperature ranges without having to change power supply or signal bias voltages. The following link details this benefit and its physics as measured on an earlier generation 6H-SiC prototype ICs.
Assessment of Durable SiC JFET Technology for +600 °C to -125 °C Integrated Circuit Operation, Electrochemical Society Transactions, vol. 41, no. 8, p. 163 (2011). 

In addition to digital logic, SiC JFET-R also implements analog and mixed-signal ICs including operational amplifiers and analog to digital converters (ADC). The online NASA Technical Memorandum, “Practical SiC JFET-R Analog Integrated Circuit Design for Extreme Environment Applications” provides a detailed tutorial for building temperature-compensated SiC JFET-R analog circuit designs including numerous circuit examples (such as operational amplifiers) and SPICE simulations.

Experimental Results

This section links to publications describing the major performance accomplishments and characteristics of NASA Glenn SiC JFET-R ICs from the Version 10 run (including ring oscillators, differential amplifiers, flip-flops, memory).

• Demonstration of 4H-SiC JFET Digital ICs Across 1000 °C Temperature Range Without Change to Input Voltages, Materials Science Forum, vol. 963, p. 813 (2019).
  
• Demonstration of 4H-SiC Digital Integrated Circuits Above 800 °C, IEEE Electron Dev. Lett., vol. 38, p. 1082 (2017).
• Yearlong 500 °C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits, Proc. 2018 IMAPS High Temperature Electronics Conference, p. 71.
• Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to Venus Surface Atmospheric Conditions, IEEE J. Electron Devices Soc., vol. 7, p. 100 (2018).